Passive electronic device

ABSTRACT

A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.

FIELD OF THE INVENTION

The present invention is related to an interposer device. More specifically, the present invention is related to an interposer device which allows for direct capacitance decoupling for decreased inductance combined with electronic filtering of microprocessor feed power in a minimized device footprint.

BACKGROUND OF THE INVENTION

Integrated circuits (IC) containing decoupling capacitors are commonly employed in virtually all modem electronic systems. Decoupling capacitors are typically mounted between power and ground circuits to reduce noise to the IC. For the purposes of the present invention an integrated circuit may be a discrete element or it may be incorporated into an integrated circuit package wherein the IC package comprises additional functioning elements.

The location of decoupling capacitors has become increasingly more important as the clock speed, or switching frequencies, of modem IC's has increased. With low clock speeds, such as hundreds of kilohertz to tens of megahertz, the location is of less significance. As clock speeds approach hundreds of megahertz or higher it becomes imperative to minimize the inductance of the decoupling circuit traces such that parasitic inductance is minimized. Parasitic inductance has been reduced markedly by optimization of the component design, as well as positioning of the decoupling capacitors nearer to the IC and with use of smaller capacitors having lower inductance values. As clock speeds increase further these prior improvements will be less suitable for high speed decoupling as the associated parasitic inductances associated with these methods has largely been minimized.

Capacitive interposers situated between the IC and printed circuit board (PCB) have improved the parasitic inductance as indicated in U.S. Pat. No. 6,961,231. A capacitive interposer has an array of lands on each surface. The IC, or IC package, is coupled to the interposer at the lands on one surface of the interposer. The PCB is coupled to the capacitive interposer at lands on the opposite side of the interposer. Electrically conductive vias in the capacitive interposer interconnect the lands with terminals on the opposite side. Capacitors are mounted on, or incorporated into, the capacitive interposer thereby providing the decoupling function desired.

Capacitive interposers are relatively thin and typically do not add significantly to the overall size of the electronic package. It is typical in the electronics industry that each generation of advancement in electronic devices demands higher clock speeds, smaller size and increased functionality. This ongoing demand requires even further reduction in size as well as in decreases in parasitic inductance.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide improvements in capacitive interposers.

It is another object of the present invention to provide an interposer which provides power directly through capacitors thereby reducing the incidence of unwanted high frequency signals (or noise) on the power sent directly to the IC as the capacitors are configured for an electronic filtering function as well as for decoupling.

A particular feature of the present invention is the ability to increase the functionality of a capacitive interposer without an increase in the spatial footprint requirement for the IC or IC package.

These and other advantages, as will be realized, are provided in an interposer. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. Each capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. Each capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.

Yet another embodiment is provided in an electronic package. The electronic package has an integrated circuit with an array of IC contacts, a printed circuit board with an array of PCB contacts and an interposer between the integrated circuit and the printed circuit board. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. Each capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are in direct electrical contact with one of the array of IC contacts and the array of the PCB contacts. The lower connections are in electrical contact with one of the array of IC contacts and the array of PCB contacts different from the upper connections.

Yet another embodiment is provided in an electronic device. The electronic device has an electronic package with an integrated circuit having an array of IC contacts, at least one printed circuit board with an array of PCB contacts and an interposer between the integrated circuit and the printed circuit board. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates. At least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, the first external termination and the second external termination are in direct electrical contact with one of the array of IC contacts and the array of PCB contacts. The lower contact pads are in electrical contact with one of the array of IC contacts and the array of PCB contacts different from the upper connections. A power supply is provided for supplying power to the electronic package. An input device is provided which is capable of interfacing to provide an input signal to the electronic package. An output device is provided for sending an output signal from the electronic package.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional schematic representation of an embodiment of the present invention.

FIG. 2 is a front view schematic representation of an embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 2.

FIG. 4 is a partial cross-sectional schematic view of an embodiment of the present invention.

FIG. 5 is a front view schematic representation of an embodiment of the present invention.

FIG. 6 is a cross-sectional schematic view taken along line 6-6 of FIG. 6.

FIG. 7 is a partial top view schematic representation of an embodiment of the present invention.

FIG. 8 is a partial top view schematic representation of an embodiment of the present invention.

FIG. 9 is a cross-sectional schematic representation of the present invention.

FIG. 10 is a schematic representation of a capacitor of the present invention.

FIG. 11 is a schematic representation of a capacitor of the present invention.

FIG. 12 is a schematic representation of a capacitor of the present invention.

DETAILED DESCRIPTION

The present invention will be described with reference to the various figures representing preferred embodiments without limit thereto. In the figures, similar elements are numbered accordingly.

An interposer is typically between an IC and a PCB with connectivity passing through the interposer thereby forming an electronic package. The electronic package is then utilized in an electronic device. An electronic device is illustrated in cross-sectional schematic view in FIG. 1. In FIG. 1, the electronic device, generally represented at 100, comprises a power source, 102, an input element, 103, an output element, 104, and an electronic package, 105.

The power source, input device and output device are not limited herein. The power source provides power to operate the components and elements of the electronic device.

The input device is any device which contains or provides a signal upon which an action is taken by another electronic device. The input device may be a storage device, an active electronic device, other circuitry or it may be a device which allows input from an external source such as a terminal, detector, receiver, or the like.

The output device is any device which reports a result. The report can be in the form of a digital or analog audible or visual signal or it may be an electrical, mechanical or electromechanical signal.

In combination, the power source, input device, output device and electronic package generally represent the predominant components of an electronic device which perform a function. The function performed by the electronic device is not limited herein.

The electronic package, 105, comprises an integrated circuit, 106, and printed circuit board, 107, with an interposer, 108, there between. A multiplicity of connectors, 109, provides electrical connectivity between the IC and PCB. Some of the connectors may pass through the interposer for direct electrical connection between the IC and PCB. Other connectors incorporate functional connectivity with the interposer wherein the interposer provides some function to the overall electronic package.

An interposer of the present invention is represented in front view in FIG. 2 and in cross-sectional view taken along line 3-3 in FIG. 3. The interposer, generally represented at 20, comprises a substrate, 21. A multiplicity of capacitors, 22, are mounted on the face of the substrate. At least one capacitor comprises external terminations, 26, which are in electrical contact through conductive vias or the like with a connector, 27, on the opposite face from that on which the capacitor is mounted. Connectors on the same side of the interposer as the capacitor, 23, provide connectivity to an IC or PCB. Sockets, 25, are preferably arranged opposite to the connectors, 23, and are in electrical contact through conductive vias or the like. In FIG. 3, the connectors are illustrated as pins and socket connectors with the understanding that other connectors, such as solder balls and solder pads or the like, may be incorporated as well. In use, the pins would typically be received by sockets of the IC or PCB or by a land grid array (LGA) of terminal pads and the termination of the capacitor would be in contact with pads of the IC or PCB. The sockets, 25, would receive pins from an IC or PCB. Therefore, the interposer is situated between the IC and PCB with electrical conductivity directly through the interposer, either via signal circuits or directly through at least one of the capacitors.

In a particularly preferred embodiment power from the PCB to the IC passes directly through the capacitor(s) for select components on the IC. In a particularly preferred embodiment at least one pin is a signal pin to a component and the component receives power through one external termination of a capacitor and is grounded through at least one external termination of, preferably, the same capacitor. This provides direct decoupling without the necessity of dedicated circuit traces on or in the interposer. Elimination, or reduction, of the circuit traces dedicated to power and decoupling of power provides a substantial spatial benefit and decreases parasitic inductance.

At least one pair of opposing connectors is a functional connection, 24. A functional connection alters the signal passing there through by functioning as at least one of a resistor, an inductor or a varistor. By providing functional connectors select elements which would normally reside on either the IC or PCB can be eliminated due to the functionality being provided by the functional connection there between. At least one of the pair of opposing connectors can be a signal interconnect having minimal resistance or impedance properties specifically tailored to the frequency and voltage intended for signal conduction.

A partial cross-sectional view of an embodiment of the invention is illustrated in FIG. 4. In FIG. 4 the substrate, 21, has mounted thereon a capacitor, 22. The capacitor has external terminations, 26. Each capacitor has at least two external terminations and at least two external terminations are of opposing polarity. A PCB, 31, is mounted below the interposer with connectors, 35, in direct electrical contact with a connector, 23, and each external termination, 26, of the capacitor 22. A signal trace, 32, of the PCB provides a signal to a component, 28, of the IC through the conductive path formed by the connectors, 35, 23, 30 and 27. Power is supplied from a power trace, 33, and ground trace, 34, through the external terminations of the capacitor, 22, and the respective connectors. In this configuration power is supplied directly through the terminations, 26, of the capacitor and directly through conduction paths, 30, of the interposer. By directly coupling the power through the capacitor the power and ground are decoupled, as well as electronically filtered. This direct decoupling reduces or eliminates the necessity of dedicated connectors and circuit traces between the capacitor and the dedicated connectors thereby minimizing the footprint of the interposer as well as simplifying subsequent assembly of the configuration.

It is preferred that the interposer have the same connector arrangement as the IC and PCB such that the interposer can be positioned between the IC and PCB with minimal increase in total circuit volume.

An interposer of the invention is represented in front view in FIG. 5 and in cross-sectional view taken along line 6-6 in FIG. 6. The interposer, generally represented at 50, comprises a substrate, 21. A multiplicity of capacitors, 51, are integral to the substrate such that each capacitor termination, 52, is accessible above and below the substrate. Each capacitor termination is directly coupled to the IC, or IC package, on one side and PCB on the other such that the circuit path is directly through at least one capacitor. The remaining connections, 53, are preferably a ball grid array (BGA). The interposer comprises a conduction path, 54, passing there through such that solder balls on opposing sides are electrically connected. It is preferred that at least one conduction path is a signal conduction path. In one embodiment at least one conduction path, 54, is a functional conductive path which is at least one of a resistive connector, an inductive connector and a varistor connector.

An embodiment of the invention is illustrated in partial top view in FIG. 7. In FIG. 7, the interposer, 80, comprises rows, 81, and columns, 82, of connectors interrupted by capacitors, 83. The capacitors are arranged such that each capacitor is offset by at least one row and at least one column from each adjacent capacitor. An adjacent capacitor is the closest capacitor in a row or column. By offsetting each capacitor by at least one row and at least one column the cross-talk between signal or functional input/outputs (I/Os) may be significantly reduced.

Another embodiment of the invention is illustrated in partial view in FIG. 8. In FIG. 8 the interposer, 80, rows, 81, columns, 82 and capacitors are as described relative to FIG. 7. In each case the adjacent capacitors are offset by at least one row and by at least one column.

The terms above, below, upper and lower are relative non-limiting terms used for clarity in discussion which could be reversed without consequence.

The configuration of multilayer capacitors is well known in the art. With reference to FIG. 9, an exemplary structure of a multilayer ceramic chip capacitor, 1, is shown. External electrodes, 2 and 2′, forming the terminations of the capacitor, 1, are disposed on side surfaces of the capacitor block structure, 1, and in electrical connection to internal electrode layers, 3 and 4. The capacitor chip, 1, has a plurality of stacked electrode layers, 3 and 4, such that alternating electrodes extend to opposite external electrodes. A dielectric material, 5, interleaves these internal electrode layers forming an insulative and electrical field enhancement between the areas created by these overlapping electrode planes.

Connectors as referred to herein include all standard connective techniques employed between an IC, or IC package, and a PCB with, or without, an interposer there between. Without limit connectors refer to solder pads, land grid arrays, ball grid arrays, controlled collapse chip connection (C4), pin, socket and combinations thereof.

The conduction path in the interposer refers to any structure which allows current to flow from a connector on one face to a conductor opposite thereto. It is preferred that the conduction path span the shortest distance between the opposing connectors.

A resistive connector partially opposes passage of electrical current. The application in circuitry is well known to those of skill in the art. For the purposes of the present invention a resistive connector has a resistance of at least 10⁻⁶ ohm to no more than 10¹⁰ ohm.

An inductive connector increases inductance, or magnetic flux, which opposes changes in current. For the purposes of the present invention an inductive connector has an inductance of at least 1 pH to no more than 1 H.

A varistor connector is an electronic connection with significant non-ohmic current-voltage characteristics. A varistor, also referred to as a voltage dependent resistor or variable resistor, shunts current created by high voltage away from sensitive components.

The capacitor is preferably prepared as described in U.S. Pat. No. 7,068,490 which is incorporated herein by reference. As illustrated in FIG. 10 individual dielectric layers or material, 401, are stacked in a multilayer fashion with the electrode patterns, 402, creating the capacitive layers and edge connectors at the top and bottom of the device. The electrode pattern, 402, is created to allow the multiple edge connectors on the same plate to terminate to non-adjacent termination pads, 406 or 407, with adjacent termination pads connecting to adjacent electrode layers. The stacking arrangement is completed to as maximum a depth, 405, as required for the application of interest. The stacked layers are then pressed (and fired if ceramic) into a singular element, 301, referred to herein as subunits. Termination pads at the top and bottom faces of the element are formed as known in the art. The termination pads are created as metallic contacts that allow connection to the circuit, as well as connecting the non-adjacent electrodes of the stack, 404, into a common or parallel arrangement. The common electrical state of the opposing termination pads is preferred for two purposes; they allow the shortest possible path for the current to feed through the device and they allow the shortest possible path for heat conduction through the device. The current feed in (408) and out (409) through the device is shown by arrows.

The requirements of decoupling state of the art IC-based microprocessors demand a great deal of charge availability virtually instantaneously in order to ensure stability of current to the IC. This requires a substantial amount of capacitance local to the IC with minimal impedance (inductance) in the current path to the IC. As such, the device may not be sufficient to handle the current through the limited pad arrangements on each face, but could be mounted as multiple singular elements, or as assembled multiple units. In FIG. 11( a), four elements, 301, distinguished by dotted lines, are bonded or arranged together to create a larger device, 601, with broader linear contacts, 602 and 603. This assembly can be fabricated either by bonding or arranging multiple units, 301, together after each element has reached a final state, or assembled before the termination pads are applied. For ceramic chips, this structure could even be created with green chips using ceramic slurry or the like as an adhesive before the final sintering for the ceramic dielectric. Alternatively, an adhesive, or molding operation, or assembly to a frame and the like can be incorporated after sintering of the subunits. The plate designs, typically referred to as “A” and “B” plates, are illustrated in FIGS. 11( b) and 11(c) which, when taken together, form the internal electrode plates of the element, 310. Four subunits are illustrated in exploded view in FIG. 11( d) wherein the subunits are taken together to form the capacitor of FIG. 11( a).

In FIG. 12( a), the assembly, 801, of individual elements, 301, has a bonding agent, 802, between the elements to allow a separation or isolation of the termination pads from one element to the other. This arrangement allows for a fully interdigitated matrix of “power” and “ground” termination pads for the assembly, 801. The capacitor of FIG. 12( a) is shown in side view in FIG. 12( b). The bonding agent can be any suitable adhesive including organic adhesives, molded thermoplastics, molded thermosets, or the like or a combination thereof, or ceramic slurry adhesives or the like or any combination thereof.

It is preferred that the capacitor is mounted to the interposer with the internal plates perpendicular to the face of the interposer surface.

This structure could also be utilized in electrolytic capacitors where the dielectric would be formed as an anodization on each electrode plate, or alternate electrode plates, and the dielectric in this structure is replaced by a conductive or semiconductive material. The electrode with the anodization would create the anode contact or termination, and the opposing termination would create the cathode termination. By anodizing adjacent electrode plates, a non-polar electrolytic could also be created. A desired capacitor circuit is completed in this way.

The subunits are typically about 0.1 to 2 mm wide and 0.11 to 4 mm thick (excluding termination pads) and 1 to 10 mm long. Typically about 2 to 200 subunits are combined into the assembly with about 100 being preferred. The termination pads are separated by a sufficient distance to avoid arcing between pads as well as to accommodate the terminal pad spacing of the top and bottom circuits of assembly (typically the IC package on top and the PCB on the bottom). A separation of at least about 0.005 mm is preferred with 0.5 mm to 1 mm being more preferred.

The dielectric layers may have any desired mean grain size. By limiting the dielectric material to the above-defined composition, there are obtained fine crystal grains which typically have a mean grain size of about 0.05 to about 3.0 μm.

The dielectric layers have an appropriate Curie temperature which is determined in accordance with the applicable standards by suitably selecting a particular composition of dielectric material. Typically the Curie temperature is higher than 45° C., especially about 65° C. to 125° C.

Each dielectric layer preferably has a thickness of up to about 50 μm, more preferably up to about 10 μm. The lower limit of thickness is about 0.2 μm, preferably about 1.5 μm. The number of dielectric layers stacked is generally from 2 to about 500, preferably from 50 to about 250.

The conductor which forms the internal electrode layers is not critical, although a base metal preferably is used since the dielectric material of the dielectric layers has anti-reducing properties. Typical base metals are nickel, copper, titanium, tungsten, molybdenum, alloys or cermets of base metals or base metal alloys with nickel being preferred. Preferred nickel alloys are alloys of nickel with at least one member selected from Cu, Si, Ba, Ti, Mn, Cr, Co, and Al, with such nickel alloys containing at least 95 wt % of nickel being more preferred. It is to be noted that nickel and nickel alloys may contain up to about 0.1 wt % of phosphorous and other trace components.

The thickness of the internal electrode layers may be suitably determined in accordance with a particular purpose and application although its upper limit is typically about 5 μm, preferably about 2.5 μm, and its lower limit is typically about 0.2 μm, preferably about 1.3 μm.

The conductor which forms the external electrodes is not critical, although inexpensive metals such as nickel, copper, and alloys thereof are preferred. The thickness of the external electrodes may be suitably determined in accordance with a particular purpose and application although it generally ranges from about 5 μm to about 100 μm.

The multilayer ceramic chip capacitor of the present invention generally is fabricated by forming a green chip by conventional printing and sheeting methods using pastes, firing the chip, and printing or transferring external electrodes thereto followed by baking.

Paste for forming the dielectric layers can be obtained by mixing a raw dielectric material with an organic or aqueous vehicle. The raw dielectric material may be a mixture of oxides and composite oxides as previously mentioned. Also useful are various compounds which convert to such oxides and composite oxides upon firing. These include, for example, carbonates, oxalates, nitrates, hydroxides, and organometallic compounds. The dielectric material is obtained by selecting appropriate species from these oxides and compounds and mixing them. The proportion of such compounds in the raw dielectric material is determined such that after firing, the specific dielectric layer composition may be met. The raw dielectric material is generally used in powder form having a mean particle size of about 0.1 to about 3 μm, preferably about 0.5 μm. Dielectrics are well known and not limited herein.

The vehicle is a binder in solvent. The binder used herein is not critical and may be suitably selected from conventional binders such as ethyl cellulose or the like. Also the solvent used herein is not critical and may be suitably selected from conventional solvents such as water, terpineol, butylcarbinol, acetone, and toluene in accordance with a particular application method such as a printing, coating or sheeting method.

Paste for forming internal electrode layers is obtained by mixing an electro-conductive material with an organic or aqueous vehicle. The conductive material used herein includes conductors such as conductive metals and alloys as mentioned above and various compounds which convert into such conductors upon firing, for example, oxides, organometallic compounds and resinates. The organic vehicle is as mentioned above.

Paste for forming external electrodes is prepared by the same method as the internal electrodes layer-forming paste.

No particular limit is imposed on the vehicle content of the respective pastes mentioned above. Often the paste contains about 1 to 5 wt % of the binder and about 10 to 50 wt % of the solvent. If desired, the respective pastes may contain any other additives such as dispersants, plasticizers, dielectric compounds, and insulating compounds. The total content of these additives is preferably up to about 10 wt %.

A green chip then may be prepared from the dielectric layer-forming paste and the internal electrode layer-forming paste. In the case of printing method, a green chip is prepared by alternately printing the pastes onto a substrate of polyethylene terephthalate (PET), for example, in laminar form, cutting the laminar stack to a predetermined shape and separating it from the substrate.

Also useful is a sheeting method wherein a green chip is prepared by forming green sheets from the dielectric layer-forming paste, printing the internal electrode layer-forming paste on the respective green sheets, and stacking the printed green sheets.

The binder is then removed from the green chip and fired. Binder removal may be carried out under conventional conditions, preferably under the following conditions where the internal electrode layers are formed of a base metal conductor such as nickel and nickel alloys.

The heating rate may be 1 to 300° C./hour and more preferably 2 to 100° C./hour. The holding temperature may be 200 to 900° C. and more preferably 220 to 300° C. The holding time may be ½ to 100 hours and more preferably 2 to 20 hours. The atmosphere is preferably air but may contain mixtures of air, hydrogen and nitrogen. The green chip is fired in an atmosphere which may be determined in accordance with the type of conductor in the internal electrode layer-forming paste. Where the internal electrode layers are formed of a base metal conductor such as nickel and nickel alloys, the firing atmosphere may have an oxygen partial pressure of 10⁻³ to 10⁻¹⁸ atm. Extremely low oxygen partial pressure should be avoided, since at such low pressures the conductor can be abnormally sintered and may become disconnected from the dielectric layers. At oxygen partial pressures above the range, the internal electrode layers are likely to be oxidized.

For firing, the chip preferably is held at a temperature of 1,000° C. to 1,400° C., more preferably 1,100 to 1,400° C. Lower holding temperatures below the range would provide insufficient densification whereas higher holding temperatures above the range can lead to poor DC bias performance. Remaining conditions for sintering preferably are as follows. The heating rate may be 5 to 500° C./hour and more preferably 20 to 300° C./hour. The holding time may be 0.1 to 24 hours and more preferably 1 to 3 hours. The cooling rate may be 5 to 500° C./hour and more preferably 200 to 300° C./hour. The firing atmosphere is preferably a reducing atmosphere. An exemplary atmospheric gas is a humidified mixture of N₂ and H₂ gases.

Firing of the capacitor chip in a reducing atmosphere preferably is followed by annealing. Annealing is effective for re-oxidizing the dielectric layers, thereby optimizing the resistance of the ceramic to dielectric breakdown. The annealing atmosphere may have an oxygen partial pressure of at least 10⁻⁸ atm., preferably 10⁻⁵ to 10⁻⁴ atm. The dielectric layers are not sufficiently re-oxidized at partial pressures below the range, whereas the internal electrode layers are likely to be deleteriously oxidized at oxygen partial pressures above this range.

For annealing, the chip preferably is held at a temperature of lower than 1,100° C. and more preferably 500° C. to 1,000° C. Lower holding temperatures below the range would oxidize the dielectric layers to a lesser extent, thereby leading to a shorter life performance of the chip. Higher holding temperatures above the range can cause the internal electrode layers to be oxidized (leading to a reduced capacitance) and to react with the dielectric material (leading to a shorter life performance). Annealing can be accomplished simply by heating and cooling. In this case, the holding temperature is equal to the highest temperature on heating and the holding time is zero. Preferred conditions for annealing include a holding time of 0 to 80 hours, more preferably 6 to 10 hours, and a cooling rate or 5 to 500° C./hour and more preferably 100 to 300° C./hour.

The preferred atmospheric gas for annealing is humid nitrogen gas. The nitrogen gas or a gas mixture used in binder removal, firing, and annealing, may be humidified using a wetter. In this regard, water temperature preferably is about 5 to 75° C.

The binder removal, firing, and annealing may be carried out either continuously or separately. If done continuously, the process includes the steps of binder removal, changing only the atmosphere without cooling, raising the temperature to the firing temperature, holding the chip at that temperature for firing, lowering the temperature to the annealing temperature, changing the atmosphere at that temperature, and annealing.

If done separately, after binder removal and cooling down, the temperature of the chip is raised to the binder-removing temperature in dry or humid nitrogen gas. The atmosphere then is changed to a reducing one, and the temperature is further raised for firing. Thereafter, the temperature is lowered to the annealing temperature and the atmosphere is again changed to dry or humid nitrogen gas, and cooling is continued. Alternately, once cooled down, the temperature may be raised to the annealing temperature in a nitrogen gas atmosphere. The entire annealing step may be done in a humid nitrogen gas atmosphere.

The resulting chip may be polished at end faces by barrel tumbling and sand blasting, for example, before the external electrode-forming paste is printed or transferred and baked to form external electrodes. Firing of the external electrode-forming paste may be carried out under the following conditions: a humid mixture of nitrogen and hydrogen gases, about 600 to 800° C., and about 10 minutes to about 1 hour.

Pads are preferably finished on the external electrodes by plating or other methods known in the art.

The multilayer ceramic chip capacitors are then assembled into an array configuration as described, via means of adhesion, molding, overmolding, framing or other suitable ganging processes. The functional and conductive circuit elements are added to the ganged capacitive device either concurrently or subsequently to ganging of the capacitive units, using frame array technology or other means suitable to achieving the desired array configuration. The invention can be mounted on printed circuit boards, for example, by soldering or by electrically conductive adhesive (ECA) attach or by mechanical interconnect as in the case of a removable connector.

The present invention has been described with particular reference to the preferred embodiments. It would be apparent from the description herein that other embodiments could be realized without departing from the scope of the invention which is set forth in the claims appended hereto. 

1. An interposer comprising: a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising: a plurality of parallel plates with a dielectric there between; at least one first external termination in electrical contact with a first set of alternate parallel plates; and at least one second external termination in electrical contact with a second set of alternate parallel plates; said capacitor is electrically or physically connected to said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection; and at least one upper connection, said first external termination and said second external termination arranged for direct electrical contact with element contact pads of a common element.
 2. The interposer of claim 1 wherein said common element is selected from an integrated circuit and a printed circuit board.
 3. The interposer of claim 2 further comprising one of an integrated circuit, an integrated circuit package and a printed circuit board in direct electrical contact with said lower pads.
 4. The interposer of claim 1 wherein at least one said upper connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
 5. The interposer of claim 1 wherein at least one said lower connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
 6. The interposer of claim 1 wherein at least one conduction path of said conduction paths is a functional conduction path.
 7. The interposer of claim 6 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
 8. The interposer of claim 7 wherein said resistor has a resistance of at least 10⁻⁶ ohm to no more than 10¹⁰ ohm.
 9. An electronic package comprising the interposer of claim
 7. 10. An electronic device comprising the interposer of claim
 7. 11. The interposer of claim 1 wherein said array of upper connections comprises rows and columns.
 12. The interposer of claim 11 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
 13. The interposer of claim 1 wherein said parallel plates are perpendicular to said first planar face.
 14. An electronic package comprising: an integrated circuit comprising an array of IC contacts; a printed circuit board comprising an array of PCB contacts; and an interposer between said integrated circuit and said printed circuit board comprising: a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising: a plurality of parallel plates with a dielectric there between; at least one first external termination in electrical contact with a first set of alternate parallel plates; and at least one second external termination in electrical contact with a second set of alternate parallel plates; said capacitor is mounted on said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection; at least one upper connection, said first external termination and said second external termination are in direct electrical contact with one of said array of IC contacts and said array of PCB contacts; and said lower connections are in electrical contact with one of said array of IC contacts and said array of PCB contacts different from said upper connections.
 15. The electronic package of claim 14 wherein at least one said upper connection comprises at least one of a pin a land grid, a wire bond, a socket, a solder pad or a solder ball.
 16. The electronic package of claim 14 wherein at least one said lower connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
 17. The electronic package of claim 14 wherein at least one conduction path of said conduction paths is a functional conduction path.
 18. The electronic package of claim 17 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
 19. The electronic package of claim 17 wherein said resistor has a resistance of at least 10⁻⁶ ohm to no more than 10¹⁰ ohm.
 20. An electronic device comprising the electronic package of claim
 18. 21. The electronic package of claim 14 wherein said array of upper connections comprises row and columns.
 22. The electronic package of claim 21 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
 23. The electronic package of claim 14 wherein said parallel plates are perpendicular to said planar face.
 24. An electronic device comprising: an electronic package comprising: an integrated circuit comprising an array of IC contacts; a printed circuit board comprising an array of PCB contacts; and an interposer between said integrated circuit and said printed circuit board comprising: a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising: a plurality of parallel plates with a dielectric there between; at least one first external termination in electrical contact with a first set of alternate parallel plates; and at least one second external termination in electrical contact with a second set of alternate parallel plates; said capacitor is mounted on said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection; at least one upper connection, said first external termination and said second external termination are in direct electrical contact with one of said array of IC contacts and said array of PCB contacts; and said lower contact pads are in electrical contact with one of said array of IC contacts and said array of PCB contacts different from said upper connections; a power supply for providing power to said electronic package; an input device capable of interfacing to provide an input signal to said electronic package; and an output device capable of sending an output signal from said electronic package.
 25. The electronic device of claim 24 wherein at least one said upper connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
 26. The electronic device of claim 24 wherein at least one said lower connection comprises at least one of a pin, a land grid, a wire bond, a socket, a solder pad or a solder ball.
 27. The electronic device of claim 24 wherein at least one conduction path of said conduction paths is a functional conduction path.
 28. The electronic device of claim 27 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
 29. The electronic device of claim 28 wherein said resistor has a resistance of at least 10⁻⁶ ohm to no more than 10¹⁰ ohm.
 30. The electronic device of claim 24 wherein said array of upper connections comprises row and columns.
 31. The electronic device of claim 30 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections.
 32. The electronic device of claim 24 wherein said parallel plates are perpendicular to said first planar face.
 33. An interposer comprising: a first planar face and a second planar face; an array of upper connections on said first planar face and opposing lower connections on said second planar face with conduction paths between each upper connection of said upper connections and a lower connection of said lower connections; at least one capacitor comprising: a plurality of parallel plates with a dielectric there between; at least one first external termination in electrical contact with a first set of alternate parallel plates; and at least one second external termination in electrical contact with a second set of alternate parallel plates; said capacitor is electrically or physically connected to said first planar face with said first external termination in direct electrical contact with a first upper connection and said second external termination is in direct electrical contact with a second upper connection wherein said parallel plates are perpendicular to said first planar face; and at least one upper connection, said first external termination and said second external termination arranged for direct electrical contact with element contact pads of a common element.
 34. The interposer of claim 33 wherein said common element is selected from an integrated circuit and a printed circuit board.
 35. The interposer of claim 34 further comprising one of an integrated circuit, an integrated circuit package and a printed circuit board in direct electrical contact with said lower pads.
 36. The interposer of claim 33 wherein at least one said upper connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
 37. The interposer of claim 33 wherein at least one said lower connection comprises at least one of a pin, a socket, a land grid, a wire bond, a solder pad or a solder ball.
 38. The interposer of claim 33 wherein at least on one conduction path of said conduction paths is a functional conduction path.
 39. The interposer of claim 38 wherein said functional conduction path comprises at least one of a signal carrier, a resistor, an inductor and a varistor.
 40. The interposer of claim 39 wherein said resistor has a resistance of at least 10⁻⁶ ohm to no more than 10¹⁰ ohm.
 41. An electronic package comprising the interposer of claim
 39. 42. An electronic device comprising the interposer of claim
 39. 43. The interposer of claim 33 wherein said array of upper connections comprises rows and columns.
 44. The interposer of claim 43 further comprising multiple capacitors wherein each capacitor of said multiple capacitors is offset by at least one row and at least one column of said array of upper connections. 